New bonding techniques have provided high-density interconnections within and between integrated circuits and in other applications within electronic equipment. These techniques include the assembling of multichip modules which may contain several unpackaged integrated circuit (IC) chips mounted on a single substrate. One technique for assembling unpackaged IC chips in a multichip module or other circuit assemblies is flip-chip bonding.
Flip-chip bonding is achieved by providing an IC chip with a perimeter or area array of solder wettable contact pads which are the signal input/output terminals, and a matting array of solder wettable contact pads on a substrate. Prior to assembly on the substrate, either the chip, the substrate or both typically under a processing step wherein a solder bump is deposited at each contact pad of the IC chip and/or substrate. The IC chip is then oriented in an aligned manner on the substrate such that the solder bumps align with the corresponding wettable pads, or such that solder bumps on the IC chip and the substrate align with each other. Interconnect bonds are then made simultaneously by heating the solder bumps to a reflow temperature at which the solder flows and an electrically conductive joint is formed. Such a process is described in R. R. Tummula and E. J. Rymaszewski, Microelectronics Packaging Handbook, pp. 366-391 (Van Nostrand Reinhold, New York, N.Y., 1989), which is incorporated by reference herein.
Typically, the IC chip in the resulting structure is not flush against the substrate, but raised above the substrate based on the height of the formed interconnect bonds, which is typically on the order of 50 .mu.m to 100 .mu.m. Accordingly, a corresponding lowprofile gap exists between the IC chip and the substrate. After the reflow process, flux residues can remain in this formed low-profile gap as well as between the formed interconnect bonds. If not removed, the flux residues have the potential to degrade electrical performance and hinder formation of an epoxy underfill as is described below. However, the corresponding low-profile openings formed between the edges of the IC chip and the substrate hinder the flow of flux cleaning fluid into this low-profile gap. As a result, removal of flux residues is presently difficult to achieve.
Moreover, bonding of an IC chip to a substrate having different coefficients of thermal expansion can be problematic because differences in thermal expansion of the chip and substrate at elevated temperatures can produce shear forces on the interconnect bonds causing them to break. Typically, a low-elasticity epoxy underfill is added in the low-profile gap between the IC chip and the substrate to reduce such shear forces. However, because of the corresponding low-profile edge openings to the gap, it has been likewise difficult to flow epoxy into the low-profile gap to form the underfill.
Conventional methods for forming the epoxy underfill are tedious and time consuming and are a bottleneck during large scale production of many component assemblies. Moreover, such methods often produce air pockets in the epoxy located in the low-profile gap that are formed from the air displaced as the epoxy is flowed into the gap. These air pockets tend to expand when the assembly is subjected to elevated temperatures producing a separation force between the IC chip and substrate which can break the interconnections.
One known method for forming the underfill which reduces the likelihood for air pockets is to successively deposit beads of epoxy using a syringe around the edge of one or two non-parallel sides of the IC chip and allow capillary action to draw the epoxy under the chip. The structure is usually heated during this stage to 70.degree. to 100.degree. C. to reduce the viscosity of the underfill material and facilitate the capillary flow. After this gap is completely filled, a finishing border of epoxy having a height equal to that of the IC chip, typically on the order of 0.38 mm to 0.76 mm, is deposited around the chip's perimeter. The assembly is often heated to a temperature between 70.degree. C. and 90.degree. C. to lower the epoxy's viscosity and reduce the underfill formation time. However, even with such heating, each epoxy bead application typically requires approximately two minutes for IC chips having dimensions on the order of 1.5 cm by 1.5 cm. Moreover, such IC chips often require as much as six of the epoxy bead applications or approximately twelve minutes to completely fill the gap between the chip and the substrate. Such formation times are unsuitable for the large scale commercial production of component assemblies.
Thus, a need exists for an enhanced bonding technique that enables relatively fast and efficient methods for removing flux residues as well as for forming underfills.